The present invention relates to a process for forming a bump structure in an electronic circuit implementation and the bump structure and, more particularly, relates to a process for forming a bump structure for a circuit implementation in an electronic device such as IC for use in an electronic apparatus, and relates to the bump structure. Further, the present invention relates to a bump-structure forming member for forming the bump-structure, a process for manufacturing thereof, a circuit board having bumps formed thereon and a process for manufacturing thereof.
Conventionally, as a method for connecting an IC chip or the like having a plurality of connecting terminals to a printed wiring board (PWB) using the bumps in order to intensify the implementation density of an electronic circuit, land grid array (LGA) type connecting style has been known. If one surface of a chip or an intermediate board called an interposer or a substrate is loaded with an IC in order to connect a terminal or a wiring on the PWB to a wiring of a chip like the IC, the bumps for securing electrical connection with the PWB are formed on one surface of that interposer.
To construct the PWB in a high density, a multilayered board, such as a build-up board has been known. Using this, an electronic circuit component is mounted on each of both faces of a circuit board according to, for example, surface mount technology. Alternatively, in order to make conductive electric wirings of respective layers between adjacent layers or between desired layers, an interlayer connecting portion is provided via holes called via-hole provided for securing conductivity. A method of using the bumps as this interlayer connecting portion has been known (for example, Japanese Patent Application Laid-Open No. 2002-359471).
As a process for forming the bumps in these cases, for example, a process by electric plating using plating resist such as dry film resist (DFR) has been known. According to an example of this process, first, plating resist having an opening is provided on a conductive layer of copper foil or the like. Next, metal such as copper may be deposited in this opening by electric plating. By removing the plating resist after the electric plating treatment, the bumps projecting from the conductive layer are obtained.
As well as the process by the electric plating using plating resist described above, a process for forming the bump by etching has been known (for example, Japanese Patent Application Laid-Open No. 2003-309370).
An example of the process for forming the bump structure by etching will be described briefly with reference to FIG. 19.
As shown in FIG. 19(a), a multilayer metal sheet 200 is prepared. The multilayer metal sheet 200 is obtained by overlaying a wiring film forming metal layer 203 on a main surface of a bump-forming metal layer 201 via an etching barrier layer 202. As an example, the bump-forming metal layer 201 is a copper foil having a thickness of 100 μm, the etching barrier layer 202 is nickel having a thickness of 2 μm and the wiring film forming metal layer 203 is a copper foil having a thickness of 18 μm.
As shown in FIG. 19(b), an etching resist 204 is formed selectively on the surface of the bump-forming metal layer 201. As shown in FIG. 19(c), the bump-forming metal layer 201 is etched with the etching resist 204 used as a mask. After the etching, the etching resist 204 is removed as shown in FIG. 19(d). Then, the etching barrier layer 202 is etched as shown in FIG. 19(e). Consequently, a bump 205 projecting from the wiring film forming metal layer 203 is formed.
However, when a plurality of bumps is formed according to the aforementioned method by electric plating using plating resist, the height of the formed bumps may disperse because metal is deposited within each opening of the plating resist. According to this method, the height of the bump depends on the thickness of the plating resist. Some implementations of the electronic circuit need bumps having a large height. If a semiconductor chip is mounted on a printed board using, for example, a flip-chip method, the bump having a large height is desirable. However, there is a limitation in the thickness of material which constitutes the plating resist, such as DFR on market. Thus, it is difficult to raise the height of the bump.
On the other hand, the aforementioned method by etching can suppress the dispersion of the bump height more effectively than the method by electric plating, because the metal layer is etched with the etching resist used as a mask. Additionally, the above-mentioned problem originating from the height of the plating resist never occurs. However, if the bump is formed by etching, the surface of the metal layer, that is, a portion near a surface in a contact with the etching resist is etched more for the reason of the character of etching technology, and as the bottom portion of the metal layer is approached, the degree of the etching makes smaller. Thus, as shown in FIG. 19(c) to 19(e), the configuration of the bump may turn to substantially frusto-conical. As an example, if a bump about 0.1 mm in height is produced by the method by etching, the diameter of its top face is about 0.1 mm and the diameter of its bottom portion is about 0.15 mm. Therefore, if it is desired to form a bump having a larger height with respect to the diameter of the bottom portion, that is, a bump having a high aspect ratio, the method by etching has a limitation.
Additionally, there is a limitation by the etching resist. For, example, if it is intended to create a plurality of bumps in which the diameter of the top face is 0.1 mm, the height thereof is 0.1 mm and the diameter of the bottom portion is 0.15 mm according to the method by etching, it is necessary to use etching resist having a diameter of about 0.3 mm for each bump. If a plurality of the bumps is produced, it is necessary, to provide a gap which osmoses etching solution between an etching resist for forming a bump and an etching resist for forming an adjacent bump. At this time, it comes that respective bumps are located apart at least about 0.33 mm because this gap needs to be about 0.03 mm if considering the character of the DFR or the like. Therefore, the interval of the bumps, that is, the accuracy of a fine pitch is limited by the etching resist.